ASIC DFT Lead Engineer – Cisco – San Jose, CA

What You’ll do:

Responsible for implementing the ASIC Design-for-Test ( DFT ) features that
supports the in-system test, debug and diagnostics needs of the design.

You will be responsible for development of innovative DFT IP
in collaboration with the cross-functional teams, and play a key role in full
chip design integration with the testability features integrated in the RTL

Working closely with the design/design-verification and
physical design teams to enable the integration and validation of the Test
logic in all phases of the design, and back-end implementation flow.

Your team will be responsible for Innovative DFT for new
silicon device models, including silicon photonic chipsets, bare die, stacked
die and 2.5D and 3D and driving re-usable test and debug strategies.

The job requires the candidate to have good scripting skills
and the ability to design and debug with minimal oversight.

Skills :

Hands-on experience with Jtag protocols, Scan
and BIST architectures, including Logic BIST, memory BIST, IO BIST

Verification skills include, System Verilog,
UVM, Logic Equivalency checking and validating the Test-timing of the design.

Experience working with Gate level simulation,
and debug with VCS and other simulators.

Post-silicon validation and debug
experience; Ability to work with ATE patterns, P1687 debug a plus

ipting skills : Python/Perl.

Who you are:

ü BS
10 years / MS 8 years work experience preferred

ü Excellent
knowledge of latest state-of-the-art trends in DFT and test.

ü Strong
verbal communication skills

ü Ability
to thrive in a dynamic environment

Apply Here:,+CA&jk=8543424483454fe8&rtk=1bhiv48691a1m4h8&from=rss