Senior Engineer Design Enablement PEX – GLOBALFOUNDRIES – Essex Junction, VT

The RF Process Design Kit (PDK) development team seeks engineers to develop high quality Parasitic Extraction (PEX) decks and verification tools in Cadence QRC and Mentor Graphics xRC.

PEX is a critical part of RF design. In this role, you build the infrastructure for Silicon Loop Closure working with stakeholders from Spice Modeling, Process Integration, LVS, device library, and other relevant teams.

We have a strong team and an excellent training program. If you have good physics or electrical engineering background combined with solid software skills, we can teach you the job specific responsibilities.

Essential Responsibilities
:

• Set up RLC extraction flows for Test Macros; analysis of hardware data to produce statistical reports;
  
• Create high quality parasitic extraction techfiles for QRC, xRC and identified field solvers based on Design Manual and other source documentation
  
• Create appropriate mapping/interface files to enable smooth flow from LVS to PEX
  
• Work with cross-functional (TD, Modeling, Device) teams to ensure tight boundary in Model-PEX interface
  
• Partner with QA team to specify and create test structures suitable for verifying LVS and PEX files ensuring highest levels in quality and coverage for all features
  
• Actively participate in continuous improvement processes, learning and skills development
  
• Strong team member, able to work well with a global team
  
• Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs
  

Qualifications

Required Qualifications
:

• Bachelor’s Degree in technical discipline (
  
• Fluency in English Language – written & verbal (US Only)
• Good communication skills – both written and verbal
  
• Excellent technical problem solving skills
  
• Good attitude and interpersonal skills, works well in a team environment
  
• Travel: Less than 10%
  

Preferred Qualifications:

• Graduate work in Electrical engineering or physics
  
• 1+ year experience in IC design flows involving Parasitic Extraction
  
• 1+ year experience in Mentor CalibreLVS, and/or other industry-standard LVS tools
  
• Familiarity with Hardware measurements and subsequent data analysis (ability to generate statistical reports and plots)
  
• Familiarity with semiconductor manufacturing processes
  
• Experience in scripting languages – Perl, Tcl, etc
  

If you need a reasonable accommodation for any part of the employment process, please contact us by email at
[email protected]
and let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case-by-case basis. Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address.

An offer of employment with GLOBALFOUNDRIES is conditioned upon the successful completion of a background check and drug screen, as applicable and subject to applicable laws and regulations.

GLOBALFOUNDRIES is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, gender identity, national origin, disability, or protected Veteran status.

#LI-AO1